1. Field of the Invention
The present invention relates to a monitoring device, a semiconductor integrated circuit (IC), and a monitoring method which monitor a data transfer that is executed by a transferring circuit according to a transfer indication, specifically to a monitoring device, a semiconductor IC, and a monitoring method which enable to monitor, when a direct memory access (DMA) chip splits and transfers data via a direct memory access, whether a failure has occurred in the DMA chip.
2. Description of the Related Art
Recently, along with an improvement in a processing capacity of a computer, data used by the computer has ever been increasing and a lot of studies related to a storage for storing a large amount of data have been carried out. To be specific, for example, a plurality of hard disk drives (HDD) are combined to construct a disk system, called a redundant array of independent disks (RAID), which realizes high-speed, large capacity, and high reliability.
In the disk system such as the RAID, a disk array device including a plurality of disks which store therein data receives a command from a higher level device such as a host computer and carries out writing (write) or reading (read) of data. During the write or read, data transacted between the host computer and the disks is also cached in a cache memory inside the disk array device, and in subsequent processing, the data is read from the cache memory, thus generally enhancing a processing speed. Further, the host computer is connected to a channel adaptor inside the disk array device and the channel adaptor executes a data transfer between the host computer, the cache memory, and the disks.
The channel adaptor internally includes a direct memory access (hereinafter referred to as “DMA”) chip such as a large-scale integration (LSI) which controls the data transfer via the DMA. The DMA chip transfers data according to an indication (descriptor) of data transfer from a central processing unit (CPU). In other words, upon receiving the descriptor, the DMA chip transmits and receives data via a bus to the cache memory and the like, an address of the data and a data length being indicated by the descriptor.
During transmitting and receiving data, for example, the DMA chip sometimes splits and transfers the data, depending on a storage capacity of the bus or a processing status at a data transfer destination. In other words, the DMA chip includes a bus controller which controls the bus. The bus controller splits a batch of data into pieces of data of data length according to the storage capacity of the bus, and temporarily stops the data transfer based on an indication from the data transfer destination.
To be specific, as shown in FIG. 8, when transferring a packet of write data, the bus controller provided to the DMA chip splits the write data into pieces of data #1 to #4, and transfers the pieces of data to the transfer destination such as the cache memory. Further, other commands are processed during the transfer of each piece of data. As shown in FIG. 8, a transfer of read data is executed during transferring the data #2 and the data #3.
Further, a plurality of DMA circuits are included inside the DMA chip in general. For example, in a technology disclosed in Japanese Patent Application Laid-open No. 2005-115464, an arbiter carries out an adjustment (arbitration) of a transfer sequence of each DMA circuit. Accordingly, when data from one DMA circuit inside the DMA chip is split into pieces of data by the bus controller and transferred, the data transferred from the other DMA circuits is also transferred during the transfer of those pieces of data.
However, in the data transfer using the bus controller mentioned above, even if a portion of one piece of data is not transferred normally due to a failure such as a soft error and a logical disorder in the DMA chip, an error does not occur in a bus protocol and the portion in which the failure has occurred cannot be easily specified. In other words, when the bus controller splits the original data into the pieces of data and transfers the pieces of data, for example, even after occurrence of a failure such as a complete annihilation of the portion of the piece of data, an error does not occur on the bus protocol as long as the other pieces of data are transferred normally. Due to this, the error is detected only when the pieces of data are combined in the transfer destination of data and a cause of the error cannot be easily specified.
Especially, when using an already manufactured product as the bus controller of the DMA chip, because the bus controller is a black box, whether a processing in the bus controller is executed normally cannot be confirmed. Due to this, if an error is detected in the transfer destination of data, whether a failure has occurred in the DMA chip cannot be found out.